DECIMATION FILTERS WITH FINITE IMPULSE RESPONSE ARRAYS STRUCTURE OPTIMIZATIONS FOR IMPLEMENTATION IN FPGA

Abstract

The paper considers the architecture of FIR filter-resampler with buffer, which can significantly reduce the resource requirements of the FPGA. That is useful while developing the arrays of FIR-filters for signal representation in the numbers of digital bandwidths. Multiplier is selected as a key and more “scarce” resource of FPGA. The article describes the classical implementation of the FIR filter and calculated the number of multipliers required to implement it. As an alternative to the classical FIR filter decimator is proposed the implementation of the FIR filter decimator with buffer, as well as considering the issue of optimization and simulation of the proposed filter. The basis of the principles of optimization to reduce the number of multiplications of data on the filter coefficients: the first principle – the use of filter coefficients symmetrical about its center, the second principle – the use of half-band filter in which the even coefficients are zero.